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Careers

ASIC Physical Design Engineer - Shanghai - China

The candidate for ASIC Physical Design Engineer should meet the following criteria:

KEY RESPONSIBILITIES:

  • Owning, and maintaining P&R scripts for block gate netlist to GDSII
  • P&R, extraction, Power IR, EM of block level and Physical verification
  • Work with front end engineer for timing closure activities
  • P&R, extraction, Power IR, EM of block level and Physical verification
  • Work with front end engineer for timing closure activities
  • Executes all aspects of physical design flows such as floor planning, place and route, reliability checks, manufacturability checks, timing closure, noise analysis, formal verification, integration of custom circuits/layout, timing analysis, constraint generation.

REQUIREMENTS:

  • BSEE is required
  • 3+ years of ASIC/SoC Physical Design; floor planning, power grid customization, P&R, CTS, and DRC/LVS/ERC/Antenna debugging skills
  • Experience driving CTS to meet requirements
  • Experience with either one of P&R tools; Cadence EDI, or Synopsys IC Compiler
  • Proficiency using TCL, Perl and make scripting
  • Mass production experience a plus
  • Familiar with design flow of major foundries
Principals only need apply. Please forward your resume to hr@quantenna.com. Please include the job title “ASIC Physical Design Engineer - Shanghai” in the subject line.

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