Sr. Design for Test Engineer - Shanghai - China

The candidate for Sr. DFT (Design for Test) Engineer should meet the following criteria:


  • DFT (Design for Test) design for WiFi chips.
  • In charge of state of the art Design for Test flows and implementation.
  • Help to enhance ATPG/MBIST/BSCAN methodology.
  • Support silicon bring-up.
  • Work closely with the US teams.


  • At least 5 years DFT design experience
  • BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired.
  • Extensive knowledge of the DFT concept. This includes scan based testing, Scan Compression, Memory BIST, Logic BIST, and Boundary Scan. Knowledge of scan data compression methodologies.
  • Experience with test vector trouble shooting on ATE.
  • Experience with silicon bring-up.
  • Good communication and problem solving skills.
Principals only need apply. Please forward your resume to hr@quantenna.com. Please include the job title “Sr. DFT Engineer - Shanghai” in the subject line.

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