Senior Engineer, ASIC Verification, Shanghai - China

In the position of Senior Engineer, ASIC Verification, a key technical role, the ideal candidate will:

Key Responsibilities:

  • Take joint ownership of verification for Wireless MAC blocks
  • Working closely with MAC designers to define test plan
  • Analyze and debug simulation failures
  • Generates code coverage and functional coverage report
  • Run and debug gate level simulation
  • Perform the constraint assertion-based verification
  • Review and enhance Verification methodology pre-silicon verification


  • BS in Electrical Engineering with 5+ years of experience
  • Working experience with Medium Access protocols
  • Working knowledge of networking protocols, such as 802.11 and 802.3, is a plus
  • Hands on experience with simulation & debug tools
  • Fluent in verification language such as UVM/System Verilog
  • Familiar with the whole ASIC verification flow form test plan to test bench development and through final tapeout sign-off
  • Experience with various scripting languages and utilities such as Make, Perl, Python, or Tcl
  • Experience working with geographically dispersed teams

To apply, please forward your resume to hr-shanghai@quantenna.com.

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