Sr. ASIC Design Engineer - Shanghai - China

The candidate for Sr. ASIC Design Engineer should meet the following criteria:


  • ASIC design for SoC and Switch in WiFi chip.
  • Participate in development of micro architecture specification and RTL implementation of digital blocks. Responsible for all phases of design including design, verification, synthesis, timing closure, power estimation, and DFT.
  • Work closely with the California teams.
  • Support chip tape-out and bring up.


  • At least 8 years ASIC design experience.
  • BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired.
  • Familiar with Verilog and System Verilog.
  • Design experience in Switch, Gigabit Ethernet, DMA, CPU, and PCIe.
  • Design experience with bus protocol AXI, AHB, APB.
  • Working knowledge of networking protocols such as 802.3 and TCP/IP. 802.11 a plus.
  • Familiar with lint, CDC, formal verification methodologies.
  • Understanding of basic DFT concepts.
  • Hands on experience with synthesis and STA.
  • FPGA emulation experience a plus.
  • Good communication and problem solving skills.
  • Must be familiar with the ASIC design flow from specification to implementation through final tape-out sign-off.
  • Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging.
Principals only need apply. Please forward your resume to hr@quantenna.com. Please include the job title “Sr. ASIC Design Engineer - Shanghai” in the subject line.

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